Flip-chip packaging offers short interconnections between a semiconductor chip and a corresponding substrate, supports multi-layer substrate technology for high-capacitance and low-inductance power delivery and provides the most efficient cooling mechanism for heat to be dissipated from the transistor junctions to the environment. As a result of the above properties, flip-chip packaging is a natural choice for chips with significantly fast (data rates up to 100 Gigabits per second per 4-lane core) and power-hungry Serializer-Deserializer (SerDes) cores. However, increases in the density of SerDes cores per chip places limits on the use of flip-chip packaging technology. Although flip-chip packages can support the largest body sizes viably available in the semiconductor industry, adhering to stringent signal integrity requirements of an increasing number of SerDes cores per chip results in the imposition of a limit on the number of SerDes cores that can be supported by a viable package.